The present invention relates to a method of manufacturing a semiconductor memory apparatus of high integration, and more specifically, to a method of forming a plurality of unit cells and bit lines included in a cell array of a semiconductor memory apparatus.
Generally, a semiconductor is a material that belongs to a category of material intermediate a conductor and nonconductor according to classification of materials depending on electric conductivity. Although the semiconductor is similar to the nonconductor in a pure state, addition of impurities or other manipulation can increase the electric conductivity of the semiconductor. Impurities are added to the semiconductor, which is then connected to the conductor so as to be used to generate a semiconductor device such as a transistor. A semiconductor apparatus refers to an apparatus having various functions made of the semiconductor device. A semiconductor memory apparatus is a representative example of the semiconductor apparatus.
A type of semiconductor memory apparatus includes a plurality of unit cells each including a capacitor and a transistor. A double capacitor has been used to temporarily store data. A transistor has been used to transmit data between a bit line and a capacitor corresponding to a control signal (word line) using the electric conductivity of the semiconductor that changes depending on environment. The transistor has three regions including a gate, a source and a drain, where charges between the source and drain move in response to a control signal inputted to the gate. The charges between the source and the drain move through a channel region in accordance with the properties and operation of the semiconductor.
When a transistor is formed in a semiconductor substrate, a gate is formed in the semiconductor substrate, and impurities are doped at both sides of the gate to form a source and a drain. Due to increase of data capacity and integration of a semiconductor memory apparatus, the size of each unit cell is required to be smaller. That is, the design rule of the capacitor and the transistor included in the unit cell is decreased. As a result, a channel length of the cell transistor becomes shorter, which causes a short channel effect and a drain induced barrier lower (DIBL) effect that hinders a normal operation. For preventing the short channel effect and the DIBL effect, the doping concentration of the channel region has been increased to obtain a threshold voltage required in the cell transistor. However, as the design rule is decreased to less than 100 nm, the increase of the doping concentration in the channel region increases an electric field of a storage node (SN) junction to degrade a refresh characteristic of the semiconductor memory apparatus. In order to prevent the degradation of the refresh characteristic, a cell transistor having a three-dimensional structure is used. As a result, it is possible to secure a long channel length of the cell transistor vertically even as the design rule is decreased. Moreover, if the channel length of the cell transistor is secured, the doping concentration is decreased to prevent the degradation of the refresh characteristic. Hereinafter, a process for forming a saddle-type fin transistor used as a cell transistor having a three-dimensional structure is described.
FIGS. 1a to 1f are plane diagrams illustrating a mask pattern for forming a cell array included in a general semiconductor memory apparatus.
FIG. 1a shows when several masks used in forming a cell array are overlapped. Specifically, the masks used in forming a cell array include an ISO mask (see FIG. 1b) for defining an active region, a gate mask (see FIG. 1d) for defining a gate region of a cell transistor, a fin mask (see FIG. 1c) for defining a lower gate fin region of a saddle-type fin transistor as a cell transistor, a plug mask (see FIG. 1e) for defining a region where a plug contact is formed, a bit line contact mask (see FIG. 1f) for defining a region where a bit line contact is formed, and a bit line mask (see FIG. 1f) for defining a bit line.
Referring to FIG. 1a, the ISO masks are arranged in a cross-section (I-I′) of a first X-axis. The plug masks shown in FIG. 1e, the bit line contact masks and the bit line masks shown in FIG. 1f are arranged in a cross-section (II-II′) of a second X-axis. The bit line contact masks shown in FIG. 1f are arranged in a cross-section (III-III′) of a first Y-axis. The fin masks shown in FIG. 1e and the gate masks shown in FIG. 1d are not all formed in cross-sections (III-III, IV-IV′) of first and second Y axes.
Although the plug mask shown in FIG. 1e is formed in the same shape as compared to the ISO mask, the plug mask may move within a given distance (‘F’ shown in FIG. 2e) defined in the design rule toward the Y-axis. Referring to FIG. 1f, the bit line mask covers the bit line contact mask (polygonal pattern).
FIGS. 2a to 2h are cross-sectional diagrams illustrating a method for forming a cell array in the semiconductor memory apparatus using a plurality of masks shown in FIGS. 1a to 1f. 
Referring to FIG. 2a, a Shallow Trench Isolation (STI) process is performed to form a device isolation film 202 in a semiconductor substrate 201. The semiconductor substrate 201 and the device isolation film 202 are etched with the fin mask shown in FIG. 1c to form a fin region of the saddle-type fin transistor. After a gate oxide film 203 is formed over the fin region, a hard mask oxide film 206 is formed. The hard mask oxide film 206 is etched with the gate mask shown in FIG. 1d to deposit a gate electrode 204 over the etched space. After planarization, a hard mask nitride film 205 is deposited over the gate electrode 204. The hard mask oxide film 206 is etched with the gate hard mask nitride film 205 as a mask to form a gate electrode pattern. The method for forming the gate pattern of the saddle-type fin transistor has been well-known to a person having an ordinary skill in the art.
Referring to FIG. 2b, impurities are ion-implanted into the surface of the semiconductor substrate 201 through the exposed gate oxide film 203 to form a cell lightly doped drain (LDD) region. The LDD region doped with low impurities (N-) improves an operating voltage of the transistor. A cell spacer nitride film 207 is deposited over the gate oxide film 203 and the gate pattern having the LDD region. A first interlayer insulating film 208 for separating unit cells is formed over the cell spacer nitride film 207 between the gate patterns. A chemical-mechanical polishing (CMP) process is performed on the first interlayer insulating film 208 to expose the cell spacer nitride film 207. A plug hard mask film 209 is deposited over the exposed cell spacer nitride film 207 and the first interlayer insulating film 208.
After the plug hard mask film 209 is deposited, as shown in FIG. 2c, a first photoresist film 210 is formed and patterned with the plug mask shown in FIG. 1e. The plug hard mask film 209 is etched with the first photoresist film 210, and the first interlayer insulating film is removed. The cell spacer nitride film 207 is blanket-etched until the gate hard mask nitride film 205 is exposed, so that the cell spacer nitride film 207 remains only on the sidewalls of the gate pattern. The gate oxide film 203 exposed between the gate patterns is etched.
As shown in FIG. 2d, the first photoresist film 210 is removed. A polysilicon (poly Si) film 211 used as a plug is deposited over a space obtained from the etching process. A CMP process is performed on the polysilicon film 211 to expose the gate hard mask nitride film 205.
As shown in FIG. 2e, a second interlayer insulating film 212 is deposited with a given thickness over the resulting structure. A bit line contact hard mask film 213 is deposited over the second interlayer insulating film 212. A second photoresist film 214 is coated over the bit line contact hard mask film 213 and patterned with the bit line contact mask shown in FIG. 1f. The second interlayer insulating film 212 is etched with the second photoresist film 214.
As shown in FIG. 2f, the second photoresist film 214 and the bit line contact hard mask film 213 are removed to form a bit line barrier metal film 215 with a given thickness. A Rapid Thermal Annealing (RTA) process is performed on the bit line barrier metal film 215. A bit line material is deposited over the bit line barrier metal film 215 to form a bit line 216. A bit line hard mask nitride film 217 is formed over the bit line 216.
Referring to FIG. 2g, a third photoresist film (not shown) is coated over the bit line hard mask nitride film 217 and patterned with the bit line mask shown in FIG. 1f. The bit line hard mask nitride film 217, the bit line 216 and the bit line barrier metal film 215 are sequentially etched with the third photoresist film.
The bit line barrier metal film 215 is etched to form a bit line pattern. As shown in FIG. 2h, a bit line nitride film 218 is formed on sidewalls of the bit line pattern. A third interlayer insulating film 219 is deposited between the bit line patterns. A CMP process is performed on the third interlayer insulating film 219 to expose the bit line hard mask nitride film 217.
A storage node (SN) contact in the unit cell is formed over the active region where the bit line 216 is not formed. A capacitor and a line including a metal layer are formed over the SN contact to obtain a cell array in the semiconductor memory apparatus.
As the integration of the semiconductor memory apparatus is required to be higher, it is difficult to secure the minimum separation distance in order to prevent mis-operations of the lines and devices of the semiconductor memory apparatus. Also, the layout of devices and lines is complicated to increase the integration. Although masks with various patterns are required to obtain the layout, it is difficult to fabricate the masks with various patterns due to decrease of the design rule. In order to overcome the limitations and difficulties of the process, the ISO mask of FIG. 1b is moved toward the Y-axis direction according to a specific design to obtain the plug mask of FIG. 1e in the above described method for manufacturing a cell array of a semiconductor memory apparatus.
However, while the polysilicon film 211 is deposited over the space etched with the plug mask shown in FIG. 1e, polysilicon is over-deposited corresponding to a region ‘F’ shown in FIG. 2e. Referring to FIG. 1a, the over-deposited polysilicon film 211 is separated from the gate pattern by the gate nitride film 207 formed on the sidewalls of the gate pattern, which increases parasite capacitance between the gate pattern (that is, word line) and the bit line 216. As a result, it is difficult to sense data transmitted to the bit line 216 through the cell transistor. That is, the parasite capacitance reduces the data sensing margin of the bit line 216.
Furthermore, in the conventional method, the space for the bit line contact is formed in FIG. 2e, and the bit line is formed in FIG. 2g. The process may cause mis-alignment between the bit line contact mask and the bit line mask shown in FIG. 1f to reduce a process margin. In order to reduce defects generated in the manufacturing process of the semiconductor memory apparatus, methods for reducing the size of the bit line contact or increasing the thickness of the bit line sidewall nitride film corresponding to the mis-alignment are used to overcome the process margin. However, the reduction in the size of the bit line contact increases a bit line contact resistance of the cell transistor, and the increase in the thickness of the bit line sidewall nitride film corresponding to the mis-alignment increases a SN contact resistance. These two methods reduce an operating current of the cell transistor included in each unit cell, so that the speed of read and write operations of the semiconductor memory apparatus becomes slower. The excessive increase of the resistance may cause mis-operation.